Dynamic random access memory (DRAM) production in the early days resulted in large chips. Manufacturing of these chips, at first, was not concerned with shrinking every part down to its smallest size. At this time the open memory array was the standard design: true digit lines on one side and complement digit (also known as digit bar or digit*) lines on the opposite side, with sense amps in the middle. However, once the DRAMs reached the 256K memory density, shrinking of all features became important.
However, to push to even higher densities, like a one Megabit density, the open architecture proved to be inadequate because of the poorer signal to noise problem. As a result, the folded bit line architecture was developed. Yet, to use this architecture, the original memory cell from the open architecture could not be used. Thus, new cells were designed. There resulted a memory cell with a minimum size of eight square feature area (8F.sup.2). The folded architecture eliminated the signal to noise problems. Thus, further shrinkage of the other components on the DRAM resulted in an overall smaller DRAM package.